1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming isolation structures on FinFET semiconductor devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If there is no voltage applied to the gate electrode, no current flows through the device, ignoring undesirable leakage currents which are relatively small. However, when an appropriate voltage is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as so-called short channel effects, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a FinFET device is a 3-dimensional structure. More specifically, in a FinFET, a generally vertically positioned fin-shaped active area is formed and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a 3-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semi-conducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects.
The fins on a FinFET device are typically formed by performing an etching process through a patterned mask layer to define a plurality of trenches in a semiconducting substrate, wherein remaining silicon between the trenches are the fins. Electrical isolation of the fin structures on a FinFET device is provided in order to avoid electromagnetic interference (EMI) and/or parasitic leakage paths between various devices. One illustrative prior art technique of forming isolation structures on a FinFET device 10 is shown in FIGS. 1A-1D. As shown in FIG. 1A, and as mentioned above, a plurality of fins 18 are defined in a semi-conducting substrate 12 by performing an etching process through a patterned mask layer 14, e.g., a silicon nitride mask layer. Next, as shown in FIG. 1B, a layer of silicon dioxide 20 is deposited above the device and in the trenches between the fins 18. A chemical mechanical polishing (CMP) process is then performed on the layer of silicon dioxide 20 using the patterned mask layer 14 as a polish-stop layer, as reflected in FIG. 1C. Thereafter, an etching process is performed to reduce the thickness of the layer of silicon dioxide to the final isolation layer 20A. In some embodiments, the final isolation layer 20A may have a thickness on the order of about 10-30 nm.
Unfortunately, the final isolation layer 20A is subject to attack in many subsequent processing operations, such as various cleaning operations that typically involve using hydrofluoric acid, with resulting loss of at least some of the isolation material. In some cases, the final isolation layer 20A may be eroded to such an extent that it can no longer effectively serve its intended function. In other cases, the undesirable consumption of the final isolation layer 20A may not be uniform across the surface of the substrate 12. The resulting uneven amounts of isolation material between the fins 18 may create FinFETs with undesirable variations in electrical performance characteristics. As a specific example, in FinFET devices wherein portions of the fins 18 are merged together to form source/drain regions, variations in thickness of the isolation layer 20A can lead to the formation of source/drain regions having regions of unequal thickness on the final FinFET device which may adversely impact device performance.
The present disclosure is directed to various methods of forming isolation structures on FinFET semiconductor devices.